Conventional and sub-threshold operation regimes of CMOS digital circuits

In this paper a comparison of static and dynamic parameters of CMOS logic circuits operated in standard and sub-threshold regimes is presented. Analytic models of logic threshold voltage, logic delay and power consumption are derived for the sub-threshold operation regime. Certain analytic models analogies between these two regimes are shown. Threshold voltages of inverter, NAND and NOR logic circuits depend on the same parameters in both regimes. These circuits functional differences appear as a consequence of the drain current analytic model differences in the strong and weak inversion regimes. In both of these regimes, the inverter and transmission gate temperature characteristics are analyzed. Analytic models are verified by PSPICE simulation using the BSIM3 transistor models of the 0.18 μm CMOS technology process.